FIG. 1 illustrates a schematic block diagram of an architecture of a known computing system 10. The computing system 10 includes a central processing unit 12 integrated circuit, a North bridge 14 integrated circuit, system memory 16, a video graphics processor 18, and a South bridge 22 integrated circuit. The video graphics processor 18 includes a memory controller 54 that interfaces with a frame buffer 20. The video graphics processor 18 utilizes the frame buffer 20 to store processed pixel information for subsequent display.
The central processing unit 12 integrated circuit includes a CPU core logic 24, local cache 26, a phase lock loop 28, an interface 30, a driver 34, and a receiver 36. The driver 34 and receiver 36 are operably coupled to bus 13, which enables the central processing unit 12 to interface with the North bridge 14. The data transceived over bus 13 is done in accordance with a bus protocol. For example, a bus protocol may be DEC Alpha protocol. For a 64 bit bus, 234 pins are required on the central processing unit 12 integrated circuit and a corresponding number are required on the North bridge 14 integrated circuit. The speed at which data is transceived over bus 13 is limited by circuit board technology and in particular by the trace sizes that have a resistance and parasitic inductance and capacitance. As such, current technology enables data to be transceived between the CPU 12 and the North bridge 14 at a rate of about 200 MHz per second.
Internally, the central processing unit 12 utilizes a native bus protocol that allows the central processing unit core 24 to interface with the local cache 26 and the interface 30 at rates from 500 MHz per second to 1,000 MHz per second. In order for the central processing unit 12 to prepare data for transmission on bus 13, the interface 30 must convert the CPUs native bus protocol into the bus protocol. The interface 30 includes a first-in, first-out buffer (FIFO) 32 that is sandwiched between a core interface and a bus interface. The bus interface retrieves data from the FIFO at a rate, and in a format, corresponding to the bus protocol and the core interface retrieves data from the FIFO at a rate, and in a format, corresponding to the native bus protocol. As such, the interface 30 provides the conversion between the CPU native bus protocol and the bus protocol of bus 13.
The North bridge 14 integrated circuit includes a driver 50, a receiver 52, an interface 46, and a North bridge core logic 38. The North bridge core logic 38 includes a memory controller 40 for interfacing with system memory 16, a PCI interface 42 and an AGP (accelerated graphics port) interface 44. The AGP interface 44 enables the video graphics processor 18 to interface with system memory 16. The PCI interface 42 couples the South bridge 22 integrated circuit to the North bridge 14 via a PCI bus. The PCI bus may be a 32 bit bus thereby requiring 100 pins for connection. The AGP interface has about 100 pins and operates at 133-266 Mhz.
The driver 50 and receiver 52 within North bridge 14 perform a similar function as driver 34 and receiver 36. As such, the driver 50 and receiver 52 provide an interface with bus 13 for the North bridge 14. In essence, the drivers 34 and 50 provide the power needed to appropriately transmit the data between the central processing unit 12 and North bridge 14. Conversely, the receivers 36 and 52 include amplifiers to ensure that the data received is of appropriate digital levels.
The interface 46 performs a similar function as interface 30 by converting the bus protocol for bus 13 into a North bridge native bus protocol. Typically, the North bridge bus protocol will be that required by the system memory 16. As such, for data to be transceived between the central processing unit 12 and the North bridge 14, the data must undergo two bus protocol conversions, one from the CPU native bus protocol to the bus protocol of bus 13 and then from the bus protocol of bus 13 to the North bridge native bus protocol, which typically runs at a much lower rate than the rate of bus 13. In addition, the drivers 34 and 50 and receivers 36 and 52 require a substantial amount of power to adequately drive the bus to ensure that appropriate levels of signals are being transceived. Note that the bus protocol also costs logic gates and operational cycles.
The South bridge 22 integrated circuit includes an arbitration module 56, a USB (universal serial bus) interface 58, an ACPI module 60, a low pin count interface module 62, a PCI bridge 64, and a disk interface 66. The arbitration module 56 arbitrates between the other modules as to which module gains access to the PCI bus. The USB interface 58 provides coupling for up to four USB ports. The ACPI module 60 performs power management for the computing system. The low pin count interface 62 enables a mouse, keyboard, trackball, etc. to interface with the computing system 10. The PCI bridge 64 allows plug-in cards to interface with the computing system 10. Such plug-in cards may include an interne connection, a PC card, audio circuitry, a second graphics controller, etc. The disk interface 66, sometimes referred to as an IDE interface, allows disk drives to interface with the computing system 10. The South bridge 22 integrated circuit includes 328 pins for enabling the input/output interfaces with the computer system 10.
Currently, the central processing unit 12, the North bridge 14, the South bridge 22 and a video graphics processor 18, are fabricated as separate integrated circuits. This is primarily due to the complexity of the circuitry, which requires a substantial die size, and due to the limitations of current IC manufacturing techniques. Integration of less powerful computing systems have been achieved. For example, microcontrollers include an integration of a processor with a memory interface. However, the power of the processor is substantially less than the central processing unit 12. As such, microcontrollers are used in devices that require a specific processing function and a limited amount of processing resources. Such devices include home appliances, test equipment, etc. Microcomputers are also known to be integrated on a single integrated circuit. Such microcomputers include even less processing power than a microcontroller and provide a very simplistic computing system in comparison to the system 10 of FIG. 1.
Therefore, a need exists for a method of integrating a personal computing system and apparatus thereof that integrates a central processing unit with a North bridge, that allows the elimination of the interfacing bus, the corresponding drivers and receivers, and the pin count without loss of processing power as would result in a current microcontroller and/or microcomputer.